DesignCon 2012 Are Power Planes Necessary for High Speed Signaling?
نویسندگان
چکیده
The performance of a system depends heavily on the communication speed between integrated circuits, which is constrained by the power delivery networks (PDNs). The disruption between the power and ground planes based on the low target impedance concept induces return path discontinuities during data transitions, which create displacement current sources between the power and ground planes. These sources induce excessive power supply noise which can only be reduced by increasing the capacitance requirements through new technologies such as thin dielectrics, embedded capacitance, high frequency decoupling capacitors and other methods. The new PDN design proposed here using power transmission lines (PTLs) enables both power and signal transmission lines to be referenced to the same ground plane so that a continuous current path can be formed. Extensive simulations and measurements are shown using the PTL approach to demonstrate the enhanced signal integrity as compared to the currently practiced approaches.
منابع مشابه
DesignCon 2007 Comparison of Signaling and Equalization Schemes in High Speed SerDes (10-25Gbps)
In this paper, performance of a wide variety of signaling and equalization schemes in the SerDes system at speeds of 6Gbps, 10Gbps and higher over different type of channels are compared by using our system model tools. Pros and cons of each scheme are discussed. The trade-off between the performance and implementation is also briefly explained. Furthermore, challenges of 25G SerDes and possibl...
متن کاملDesignCon 2006 Developing a “Physical” Model for Vias
Vias in printed circuit boards (PCBs) and packages are among the components of most concern with respect to signal and power integrity in high-speed communication systems. A good amount of research has been conducted to analyze their behavior. However, when it comes to " physical " or " physics-based " understanding and modeling, vias prove to be quite elusive due to their complex environment. ...
متن کاملDesignCon 2008 Multi-level Signaling in High- density, High-speed Electrical Links
We present an analysis comparing multi-level signaling to standard NRZ signaling for module-to-module on-board electrical interconnects. To study on-board electrical performance, duobinary and PAM4 I/O models were created and compared to NRZ signaling in behavioral link-level simulations. A great variety of high-density, high-speed on-board module-to-module electrical links were analyzed, and s...
متن کاملDesignCon 2009 Broadband Methodology for Power Distribution System Analysis of Chip, Package and Board for High Speed IO Design
A broadband analysis methodology is described for the design of a power distribution system (PDS) for high-speed IO, including chip, package and board. Rather than a traditional time-domain simulation, the IO PDS is characterized through frequency domain impedances, accounting for the PDS coupling that drives simultaneous switching effects for adjacent IO cells. Chip-package-board co-simulation...
متن کاملDesignCon 2011 Worst - Case Patterns for High - Speed Simulation and Measurement
Design and validation of high speed serial link at multi Gbps requires time-domain simulation and measurement. The pattern length for transistor level simulation is limited to a few hundred bits due to the practical simulation time while the pattern length for oscilloscope measurement is limited to a few hundred to a few thousand of bits due to the record length. This is where and why " killer ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
عنوان ژورنال:
دوره شماره
صفحات -
تاریخ انتشار 2012